ST STM32WL55JC

RM0453 Rev 2 455/1454
RM0453 Direct memory access controller (DMA)
478
13.4 DMA functional description
13.4.1 DMA block diagram
The DMA block diagram is shown in Figure 49.
Figure 49. DMA block diagram
MSv61533V1
DMA2
DMA1
AHB master interface
Arbiter
Ch 1
AHB slave interface
Ch 2
Ch 7
32-bit AHB bus 32-bit AHB bus
dma1_req [1..7]
dma1_ack [1..7]
...
Interrupt
interface
dma1_it[1..7]
dma1_secm [1..7]
dma1_priv[1..7]
DMAMUX1
AHB master interface
Arbiter
Ch 1
AHB slave interface
Ch 2
Ch 7
32-bit AHB bus 32-bit AHB bus
dma2_req [1..7]
dma2_ack [1..7]
...
Interrupt
interface
dma1_ilac
dma2_ilacdma2_it[1..7]
dma2_secm [1..7]
dma2_priv[1..7]