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RM0453 Rev 2 521/1454

RM0453 Extended interrupts and event controller (EXTI)

523

16.6.12 EXTI event mask register (EXTI_CnEMR2)

Address offset: Block 1: 0x094

Address offset: Block 2: 0x0D4

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 IM46: wakeup with interrupt mask on event input 46

0: Wakeup with interrupt request from line 46 is masked.

1: Wakeup with interrupt request from line 46 is unmasked.

Bit 13 IM45: wakeup with interrupt mask on event input 45

Bit 12 IM44: wakeup with interrupt mask on event input 44

Bit 11 IM43: wakeup with interrupt mask on event input 43

Bit 10 IM42: wakeup with interrupt mask on event input 42

Bit 9 IM41: wakeup with interrupt mask on event input 41

Bit 8 IM40: wakeup with interrupt mask on event input 40

Bit 7 IM39: wakeup with interrupt mask on event input 39

Bit 6 IM38: wakeup with interrupt mask on event input 38

Bit 5 IM37: wakeup with interrupt mask on event input 37

Bit 4 IM36: wakeup with interrupt mask on event input 36

Bit 3 Reserved, must be kept at reset value.

Bit 2 IM34: wakeup with interrupt mask on event input 34

Bits 1:0 Reserved, must be kept at reset value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. EM41 EM40 Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EM41: wakeup with event generation mask on event input 41

0: Event request from line 41 is masked.

1: Event request from line 41 is unmasked.

Bit 8 EM40: wakeup with event generation mask on event input 40

Bits 7:0 Reserved, must be kept at reset value.

ST STM32WL55JC User Manual

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