ST STM32WL55JC User Manual

RM0453 Rev 2 55/1454
RM0453 List of figures
57
Figure 254. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Figure 255. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
Figure 256. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 912
Figure 257. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 913
Figure 258. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
Figure 259. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
Figure 260. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
Figure 261. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
Figure 262. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Figure 263. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . . 952
Figure 264. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
Figure 265. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 953
Figure 266. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Figure 267. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
Figure 268. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
Figure 269. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . . 974
Figure 270. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 271. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
Figure 272. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Figure 273. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
Figure 274. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
Figure 275. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Figure 276. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Figure 277. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Figure 278. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Figure 279. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Figure 280. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Figure 281. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Figure 282. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Figure 283. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Figure 284. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Figure 285. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . 1069
Figure 286. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . 1070
Figure 287. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Figure 288. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
Figure 289. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Figure 290. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
Figure 291. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Figure 292. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1076
Figure 293. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1077
Figure 294. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
Figure 295. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . 1080
Figure 296. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1081
Figure 297. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 298. Timeout intervals for t
LOW:SEXT
, t
LOW:MEXT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Figure 299. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1090
Figure 300. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1090

ST STM32WL55JC Specifications

General

Brand	ST
Model	STM32WL55JC
Category	Microcontrollers
Language	English