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Digital-to-analog converter (DAC) RM0453

610/1454 RM0453 Rev 2

19.7.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1)

Address offset: 0x0C

Reset value: 0x0000 0000

19.7.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1)

Address offset: 0x10

Reset value: 0x0000 0000

19.7.6 Dual DAC 12-bit right-aligned data holding register

(DAC_DHR12RD)

Address offset: 0x20

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

DACC1DHR[11:0] Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data

These bits are written by software.

They specify 12-bit data for DAC channel1.

Bits 3:0 Reserved, must be kept at reset value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data

These bits are written by software. They specify 8-bit data for DAC channel1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

ST STM32WL55JC User Manual

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