ST STM32WL55JC - Page 729

RM0453 Rev 2 729/1454
RM0453 Advanced-control timer (TIM1)
822
Figure 133. Counter timing diagram, internal clock divided by 4
Figure 134. Counter timing diagram, internal clock divided by N
0000 0001
0035
0036
MS31080V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
00
1F
20
MS31081V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)