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Low-power timer (LPTIM) RM0453

970/1454 RM0453 Rev 2

28.7.10 LPTIM2 option register (LPTIM2_OR)

Address offset: 0x020

Reset value: 0x0000 0000

28.7.11 LPTIM3 option register (LPTIM3_OR)

Address offset: 0x020

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OR_1 OR_0

rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 OR_[1:0]

00: input 1 is connected to I/O

01: input 1 is connected to COMP1_OUT

10: input 1 is connected to COMP2_OUT

11: input 1 is connected to COMP1_OUT OR COMP2_OUT