RM0453 Rev 2 971/1454
RM0453 Low-power timer (LPTIM)
973
28.7.12 LPTIM repetition register (LPTIM_RCR)
Address offset: 0x028
Reset value: 0x0000 0000
Caution: The LPTIM_RCR register must only be modified when the LPTIM is enabled (ENABLE bit
set to ‘1’). When using repetition counter with PRELOAD = 0, LPTIM_RCR register must be
changed at least five counter cycles before the auto reload match event, otherwise an
unpredictable behavior may occur.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition register value
REP is the repetition value for the LPTIM.
To Next Page
Loading...
Need help?
General
