Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 103
UG471 (v1.10) May 8, 2018
Rules for Combining I/O Standards in the Same Bank
MINI_LVDS_25 HR N/A N/A Yes
(3)
None None
MOBILE_DDR HR N/A SLOW, FAST Yes None None
PCI33_3 HR N/A N/A Yes None None
PPDS_25 HR N/A N/A No None None
RSDS_25 HR N/A N/A No None None
SSTL135 Both N/A SLOW, FAST Yes None None
SSTL135_R HR N/A SLOW, FAST Yes None None
SSTL135_DCI HP N/A SLOW, FAST No None Split
SSTL135_T_DCI HP N/A SLOW, FAST Required None Split
SSTL15 Both N/A SLOW, FAST Yes None None
SSTL15_R HR N/A SLOW, FAST Yes None None
SSTL15_DCI HP N/A SLOW, FAST No None Split
SSTL15_T_DCI HP N/A SLOW, FAST Required None Split
SSTL18_I Both N/A SLOW, FAST No None None
SSTL18_I_DCI HP N/A SLOW, FAST No None Split
SSTL18_II Both N/A SLOW, FAST Yes None None
SSTL18_II_DCI HP N/A SLOW, FAST Yes Split Split
SSTL18_II_T_DCI HP N/A SLOW, FAST Required None Split
TMDS_33 HR N/A N/A No None None
Notes:
1. The bidirectional buffers column describes the I/O standards use of a bidirectional signal. The standards labeled as required can
only be used with bidirectional signals and require primitives such as the IOBUF and IOBUFDS.
2. The DCI termination type column describes the type of termination available for the DCI I/O standards. Split refers to the
split-termination resistors.
3. Internal differential termination is always used in bidirectional configuration.
Table 1-56: DRIVE and SLEW Attributes, Bidirectional Buffers, and DCI Termination Type (Cont’d)
I/O Standard
I/O Bank
Availability
DRIVE (mA) SLEW
Bidirectional
Buffers
(1)
DCI Type
(2)
Outputs Outputs Outputs Inputs
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English