Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 69
UG471 (v1.10) May 8, 2018
Supported I/O Standards and Terminations
Figure 1-52 shows a sample circuit illustrating a termination technique for differential
HSTL class-II (1.5V or 1.8V) with unidirectional DCI termination. In a specific circuit, all
drivers and receivers must be at the same voltage level (either 1.5V or 1.8V); they are not
interchangeable. Only HP I/O banks support the DCI standards. The internal
split-termination resistors are always present, independent of whether the drivers are
3-stated.
X-Ref Target - Figure 1-52
Figure 1-52: Differential HSTL Class II (1.5V or 1.8V) DCI Unidirectional Termination
ug471_c1_42_121214
IOB
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18
V
CCO
=
1.5V for DIFF_HSTL_II_DCI
1.8V for DIFF_HSTL_II_DCI_18
V
CCO
=
1.5V for DIFF_HSTL_II_DCI
1.8V for DIFF_HSTL_II_DCI_18
V
CCO
=
1.5V for DIFF_HSTL_II_DCI
1.8V for DIFF_HSTL_II_DCI_18
V
CCO
=
1.5V for DIFF_HSTL_II_DCI
1.8V for DIFF_HSTL_II_DCI_18
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
+
–
DCI
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
IOB
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
R
VRN
= 2Z
0
= 100Ω
R
VRP
= 2Z
0
= 100Ω
Z
0
Z
0
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English