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Fujitsu PRIMERGY RX2520 M5

Fujitsu PRIMERGY RX2520 M5
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Error detection and correction (ECC)
Lockstep mode is not supported by BIOS on this platform
SDDC (single device data correction) for all single x4 component failures (x8
SDDC requires lockstep mode, but lockstep mode is not supported)
Channel mirroring within a CPU socket
Hardware memory scrubbing
Rank Level Sparing
The notation of the CPUs, memory channels and DIMM sockets correspond to
the silk print on the system board.
On second CPU the memory channels are named G, H, J, K, L and M and
placed accordingly
.
Figure 150: Memory slots of CPU 1
For system relevant information, see the hardware configurator of your
server available online at the following address:
https://ts.fujitsu.com/products/standard_servers/index.htm
For Japan:
https://www.fujitsu.com/jp/products/computing/servers/primergy/
10.2.2
General memory population conditions
Non-ECC DIMMs are not supported on this platform.
x4 and x8 DIMMs cannot be mixed in any channel.
Mixing of LRDIMM with RDIMM type is not allowed per platform.
Main memory
RX2520 M5 Upgrade and Maintenance Manual 259

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