15.1.1 Features ···················································································································273
15.1.2 Block Diagram ········································································································274
15.1.3 Input Pins ················································································································275
15.1.4 Register Configuration ····························································································275
15.2 Register Descriptions ·········································································································276
15.2.1 A/D Data Registers (ADDR) - H'FFE0 to H'FFE7 ·················································276
15.2.2 A/D Control/Status Register (ADCSR) - H'FFE8 ··················································277
15.3 CPU Interface ·····················································································································279
15.4 Operation ····························································································································280
15.4.1 Single Mode ············································································································281
15.4.2 Scan Mode ··············································································································284
15.5 Input Sampling Time and A/D Conversion Time ·······························································287
15.6 Interrupts and the Data Transfer Controller ·······································································289
Section 16 RAM
16.1 Overview ····························································································································291
16.1.1 Block Diagram ········································································································291
16.1.2 Register Configuration ····························································································292
16.2 RAM Control Register (RAMCR) ·····················································································292
16.3 Operation ····························································································································292
16.3.1 Expanded Modes (Modes 1, 2, 3, and 4) ································································292
16.3.2 Single-Chip Mode (Mode 7) ···················································································293
Section 17 ROM
17.1 Overview ····························································································································295
17.1.1 Block Diagram ········································································································295
17.2 PROM Modes ·····················································································································296
17.2.1 PROM Mode Setup ·································································································296
17.2.2 Socket Adapter Pin Arrangements and Memory Map ············································297
17.3 Programming ······················································································································299
17.3.1 Writing and Verifying ·····························································································299
17.3.2 Notes on Writing ·····································································································302
17.3.3 Reliability of Written Data ······················································································303
17.3.4 Erasing of Data ·······································································································304
17.4 Handling of Windowed Packages ······················································································304
Section 18 Power-Down State
18.1 Overview ····························································································································307
18.2 Sleep Mode ························································································································308
18.2.1 Transition to Sleep Mode ························································································308
18.2.2 Exit from Sleep Mode ·····························································································308
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