Section 13 Watchdog Timer
13.1 Overview ····························································································································235
13.1.1 Features ···················································································································235
13.1.2 Block Diagram ········································································································236
13.1.3 Register Configuration ····························································································236
13.2 Register Descriptions ·········································································································237
13.2.1 Timer Counter TCNT - H'FFED ·············································································237
13.2.2 Timer Control/Status Register (TCSR) - H'FFEC (Read), H'FFED (Write) ··········237
13.2.3 Notes on Register Access ························································································239
13.3 Operation ····························································································································240
13.3.1 Watchdog Timer Mode ···························································································240
13.3.2 Interval Timer Mode ·······························································································241
13.3.3 Operation in Software Standby Mode ·····································································242
13.3.4 Setting of Overflow Flag ·························································································243
13.4 Application Notes ··············································································································243
Section 14 Serial Communication Interface
14.1 Overview ····························································································································245
14.1.1 Features ···················································································································245
14.1.2 Block Diagram ········································································································246
14.1.3 Input and Output Pins ·····························································································247
14.1.4 Register Configuration ····························································································247
14.2 Register Descriptions ·········································································································247
14.2.1 Receive Shift Register (RSR) ··················································································247
14.2.2 Receive Data Register (RDR) - H'FFDD ································································248
14.2.3 Transmit Shift Register (TSR) ················································································248
14.2.4 Transmit Data Register (TDR) - H'FFDB ·······························································248
14.2.5 Serial Mode Register (SMR) - H'FFD8 ··································································249
14.2.6 Serial Control Register (SCR) - H'FFDA ·······························································251
14.2.7 Serial Status Register (SSR) - H'FFDC ··································································253
14.2.8 Bit Rate Register (BRR) - H'FFD9 ·········································································255
14.3 Operation ····························································································································259
14.3.1 Overview ·················································································································259
14.3.2 Asynchronous Mode ·······························································································260
14.3.3 Synchronous Mode ·································································································264
14.4 CPU Interrupts and DTC Interrupts ···················································································268
14.5 Application Notes ··············································································································269
Section 15 A/D Converter
15.1 Overview ····························································································································273
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