3-13 Shift Instructions ··············································································································55
3-14 Bit-Manipulation Instructions ··························································································56
3-15 Branching Instructions ·····································································································57
3-16 System Control Instructions ····························································································59
3-17 Short-Format Instructions and Equivalent General Formats ···········································62
4-1 (a) Exceptions and Their Priority ··························································································81
4-1 (b) Instruction Exceptions ······································································································81
4-2 Exception Vector Table ····································································································84
4-3 Stack after Exception Handling Sequence ·······································································94
5-1 Interrupt Controller Registers ··························································································99
5-2 Interrupts, Vectors, and Priorities ··················································································102
5-3 Assignment of Interrupt Priority Registers ····································································103
5-4 Number of States before Interrupt Service ····································································111
6-1 Internal Control Registers of the DTC ···········································································114
6-2 Data Transfer Enable Registers ·····················································································115
6-3 Assignment of Data Transfer Enable Registers ·····························································117
6-4 Addresses of DTC Vectors ·····························································································121
6-5 Number of States per Data Transfer ··············································································123
6-6 Number of States before Interrupt Service ····································································124
6-7 DTC Control Register Information Set in RAM ···························································125
7-1 Register Configuration ···································································································128
7-2 Wait Modes ····················································································································130
8-1 External Crystal Parameters ··························································································136
9-1 Input/Output Port Summary ··························································································140
9-2 Port 1 Registers ··············································································································142
9-3 Port 1 Pin Functions in Expanded Modes ······································································145
9-4 Port 1 Pin Functions in Single-Chip Modes ··································································147
9-5 Port 2 Registers ··············································································································149
9-6 Port 3 Registers ··············································································································152
9-7 Port 4 Registers ··············································································································155
9-8 Port 5 Registers ··············································································································158
9-9 Status of MOS Pull-Ups for Port 5 ················································································161
9-10 Port 6 Registers ··············································································································164
9-11 Status of MOS Pull-Ups for Port 5 ················································································167
9-12 Port 7 Registers ··············································································································168
9-13 Port 7 Pin Functions ·······································································································170
9-14 Port 8 Registers ··············································································································172
9-15 Port 9 Registers ··············································································································173
9-16 Port 9 Pin Functions ·······································································································175
10-1 Input and Output Pins of Free-Running Timer Module ················································179
10-2 Register Configuration ···································································································180
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