Hitachi H8/500 Series - Page 214

Example a: ø/4 clock source, 12-state write interval (n = 3), on-chip memory
LA: LDC.B #H'FF,BR ; Initialize base register for short-format instruction (MOV:S)
LDC.W #H'0700,SR ; Raise interrupt mask level to 7
MOV.W #m,R1 ; Data for free-running timer 1
MOV.W #m+3,R2 ; Data for free-running timer 2 (m + n = m + 3)
MOV.W #m+6,R3 ; Data for free-running timer 3 (m + 2n = m + 2 × 3)
BSR SET4 ; Call write routine
.ALIGN 2 ; Align write instructions (MOV:S) at even address
SET4:MOV:S.W R1,@H'92:8 ; Write to FRC 1 (address H'FF92) 9 states
BRN SET4:8 ; 2-Byte dummy instruction 3 states
MOV:S.W R2,@H'A2:8 ; Write to FRC 2 (address H'FFA2) Total 12 states
BRN SET4:8 ; 2-Byte dummy instruction
MOV:S.W R3,@H'B2:8 ; Write to FRC 3 (address H'FFB2)
RTS
Example b: ø/8 clock source, 16-state write interval (n = 2), on-chip memory
LB: LDC.B #H'FF,BR
LDC.W #H'0700,SR
MOV.W #m,R1
MOV.W #m+2,R2
MOV.W #m+4,R3
BSR SET8
.ALIGN 2
SET8:MOV:S.W R1,@H'92:8 ; 9 States
BRN SET8:8 ; 3 States Total 16 states
XCH R1,R1 ; 4 States
MOV:S.W R2,@H'A2:8
BRN SET8:8
XCH R2,R2
MOV:S.W R3,@H'B2:8
RTS
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