Figure 10-12 shows this type of contention.
Contention between FRC Write and Increment: If an FRC increment pulse is generated during
the T3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and
the FRC is not incremented.
Write cycle: CPU write to lower byte of FRC
T
1 T2 T3
Internal address bus
Internal write signal
FRC clear signal
ø
FRC N H’0000
FRC address
Figure 10-12 FRC Write-Clear Contention
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