Hitachi H8/500 Series - Page 350

Size CCR Bit
Mnemonic Operation B/W N Z V C
System TRAPA PC → @ – SP — — — — —
control (If MAX MODE CP → @ – SP)
SR → @ – SP
(If MAX MODE < vector > → CP)
< vector > → PC
TRAP/VS If V bit = “1” then TRAP — — — — —
else next;
RTE @ SP + → SR — ↕↕↕↕
(If MAX MODE @ SP + → CP)
@ SP + → PC
LINK FP (R6) → @ – SP — — — — —
SP → FP (R6)
SP + #IMM → SP
UNLK FP (R6) → SP — ————
@SP + → FP
SLEEP Normal running mode → power-down state — ————
LDC (EAs) → CR B/W*
STC CR → (EAd) B/W* ————
ANDC CR ∧ #IMM → CR B/W*
ORC CR ∨ #IMM → CR B/W*
XORC CR ⊕ #IMM → CR B/W*
NOP PC + 1 → PC — ————
* Depends on the CR.
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