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Hitachi H8/500 Series - Page 349

Hitachi H8/500 Series
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Size CCR Bit
Mnemonic Operation B/W N Z V C
Branch- Bcc If condition is true then
ing PC + disp → PC
instruc- else next;
tions
JMP Effective address → PC
PJMP Effective address → CP, PC
BSR PC → @ – SP
PC + disp → PC
JSR PC → @ – SP
Effective address → PC
PJSR PC → @ – SP
CP → @ – SP
Effective address → CP, PC
RTS @ SP + → PC
PRTS @ SP + → CP
@ SP + → PC
RTD @ SP + → PC
SP + #IMM → SP
PRTD @ SP + → CP
@ SP + → PC
SP + #IMM → SP
SCB If condition is true then next;
SCB/F else Rn – 1 → Rn;
SCB/NE If Rn = –1 then next;
SCB/EQ else PC + disp → PC;
Mnemonic Description Condition
BRA (BT) Always (True) True
BRN (BF) Never (False) False
BHI HIgh C Z = 0
BLS Low or Same C Z = 0
Bcc (BHS) Carry Clear (High or Same) C = 0
BCS (BLO) Carry Set (LOw) C = 1
BNE Not Equal Z = 0
BEQ EQual Z = 1
BVC oVerflow Clear V = 0
BVS oVerflow Set V = 1
BPL PLus N = 0
BMI MInus N = 1
BGE Greater or Equal N V = 0
BLT Less Than N V = 1
BGT Greater Than Z (N V) = 0
BLE Less or Equal Z (N V) = 1
Mnemonic Description Condition
SCB/F False
SCB/NE Not Equal Z = 0
SCB/EQ Equal Z = 1
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