Hitachi H8/500 Series - Page 388

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TCR—Timer Control Register H'FF90 FRT1
Bit 76543210
ICIE OCIEB OCIEA OVIE OEB OEA CKS1 CKS0
Initial value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Output Enable A
0 Compare-A output is disabled.
1 Compare-A output is enabled.
Output Enable B
0 Compare-B output is disabled.
1 Compare-B output is enabled.
Timer Overflow Interrupt Enable
0 Overflow interrupt request is disabled.
1 Overflow interrupt request is enabled.
Output Compare Interrupt Enable A
0 Compare-match A interrupt request is disabled.
1 Compare-match A interrupt request is enabled.
Output Compare Interrupt Enable B
0 Compare-match B interrupt request is disabled.
1 Compare-match B interrupt request is enabled.
Input Capture Interrupt Enable
0 Input capture interrupt is disabled.
1 Input capture interrupt is enabled.
Clock Select
00 Internal clock
source: ø4
01 Internal clock
source: ø8
10 Internal clock
source: ø32
11 External clock source:
counted on rising edge
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