380
TCSR—Timer Control/Status Register H'FF91 FRT1
Bit 76543210
ICF OCFB OCFA OVF OLVLB OLVLA IEDG CCLRA
Initial value 00000000
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W
Input Edge Select
0 Count is captured on
falling edge of input
capture signal (FTI).
1 Count is captured on
rising edge of input
capture signal.
Output Level A
0 Compare-match A causes 0 output.
1 Compare-match A causes 1 output.
Output Level B
0 Compare-match B causes 0 output.
1 Compare-match B causes 1 output.
Timer Overflow
0 Cleared from 1 to 0 when CPU reads OVF =
1, then writes 0 in OVF.
1 Set to 1 when FRC changes from H'FFFF to H'0000.
Output Compare Flag A
0 Cleared from 1 to 0 when:
1. CPU reads OCFA = 1, then writes 0 in OCFA.
2. OCIA interrupt is served by DTC.
1 Set to 1 when FRC = OCRA.
Output Compare Flag B
0 Cleared from 1 to 0 when:
1. CPU reads OCFB = 1, then writes 0 in OCFB.
2. OCIB interrupt is served by DTC.
1 Set to 1 when FRC = OCRB.
Input Capture Flag
0 Cleared from 1 to 0 when:
1. CPU reads ICF = 1, then writes 0 in ICF.
2. ICI interrupt is served by DTC.
1 Set to 1 when input capture signal is received and FRC count is copied to ICR.
Counter Clear A
0 FRC count
is not cleared.
1 FRC count is
cleared by
compare-
match A.
* Only writing of a 0 to
clear the flag is enabled.
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