Table 1-4 Pin Functions (cont)
Pin No.
CP-84,
Type Symbol CG-84 FP-80A I/O Name and Function
Interrupt NMI 22 11 I NonMaskable Interrupt: Highest-signals priority
interrupt request. The port 1 control register (P1CR)
determines whether the interrupt is requested on the
rising or falling edge of the NMI input.
IRQ
0 877 IInterrupt Request 0 and 1: Maskable interrupt
IRQ
1 9 78 request pins.
Operating MD
2 19 8 I Mode: Input pins for setting the MCU operating
mode MD
1 18 7 mode according to the table below.
control MD
0 17 6
MD
2 MD1 MD0 Mode Description
0 0 0 Mode 0 —
0 0 1 Mode 1 Expanded minimum mode
(ROM disabled)
0 1 0 Mode 2 Expanded minimum mode
(ROM enabled)
0 1 1 Mode 3 Expanded maximum mode
(ROM disabled)
1 0 0 Mode 4 Expanded maximum mode
(ROM enabled)
1 0 1 Mode 5 —
1 1 0 Mode 6 —
1 1 1 Mode 7 Single-chip mode
The inputs at these pins are latched in mode select
bits 2 to 0 (MDS2 – MDS0) of the mode control
register (MDCR) on the rising edge of the RES
signal.
18
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