Hitachi H8/500 Series - Page 428

Table C-7 (b) Port 7 Port Read (Pins P71, P72)
Setting Port Read Data
DDR = 0 Pin value
DDR = 1 DR value
RP7
P7
n
WP7
Free-running timer module
Input capture signal
WP7D:
WP7:
RP7:
n:
Write to P7DDR
Write to Port 7
Read Port 7
1 or 2
Internal data bus (PDB9 to 10)
C
R
QD
P7 DR
n
C
R1
QD
P7 DDR
n
Reset
Reset
WP7D
Figure C-7 (b) Schematic Diagram of Port 7, Pins P71 and P72
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