Intel Stratix 10 User Manual

Figure 69. TX Reset Deassertion Timing Waveform
tx_pma_ready
tx_reset_req
tx_reset_ack
tx_aib_reset
tx_transfer_ready
rsfec_reset
tx_rsfec_reset
tx_pmaif_reset
Min 100 ns
Min 100 ns
Because you only have 400 μs to complete a reset sequence, there is not enough time
to assert the reset, reconfigure the PMA, and deassert the reset. So you should assert
the reset in one reset window, reconfigure the PMA, and then deassert the reset in a
second window. Refer to Figure 70 on page 111 and Figure 71 on page 112 below for
details.
The RS-FEC block automatically locks onto the FEC symbols and you do not need to
reset the RS-FEC block through the rsfec_reset, tx_rsfec_reset, or
rx_rsfec_reset signals.
Figure 70. RX PMA Reconfiguration with Reset Controller in Manual Mode Timing
Waveform
rx_pma_ready
rx_reset_req (1)
rx_reset_ack
rx_aib_reset
rx_pmaif_reset
rx_rsfec_reset
AVMM
rx_transfer_ready
Reset and reconfigure PMA
using PMA attribute codes
Note:
1. If you have enabled the RS-FEC block, you must assert rx_reset_req after the tx_transfer_ready output is asserted.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English