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Model 2651A High Power System SourceMeter® Instrument Reference Manual Section 7: Command reference

2651A-901-01 Rev. A / March 2011 7-281

status.operation.instrument.smuX.trigger_overrrun.*

This attribute contains the operation status SMU X trigger overrun register set.

Type TSP-Link accessible Affected by Where saved Default value

Attribute - - - - - - - -

.condition (R) Yes Not applicable Not saved Not applicable

.enable (RW) Yes Status reset Not saved 0

.event (R) Yes Status reset Not saved 0

.ntr (RW) Yes Status reset Not saved 0

.ptr (RW) Yes Status reset Not saved 30 (All bits set)

Usage

operationRegister = status.operation.instrument.smuX.trigger_overrun.condition

operationRegister = status.operation.instrument.smuX.trigger_overrun.enable

operationRegister = status.operation.instrument.smuX.trigger_overrun.event

operationRegister = status.operation.instrument.smuX.trigger_overrun.ntr

operationRegister = status.operation.instrument.smuX.trigger_overrun.ptr

status.operation.instrument.smuX.trigger_overrun.enable = operationRegister

status.operation.instrument.smuX.trigger_overrun.ntr = operationRegister

status.operation.instrument.smuX.trigger_overrun.ptr = operationRegister

operationRegister

The operation status SMU X trigger overrun register's status. A zero (0) indicates no

bits set (also send 0 to clear all bits); other values indicate various bit settings

Details

These attributes are used to read or write to the operation status SMU X trigger overrun registers. Reading a

status register returns a value. The binary equivalent of the returned value indicates which register bits are set.

The least significant bit of the binary number is Bit B0, and the most significant bit is Bit B15.For example, if a

value of 18 is read as the value of the condition register, the binary equivalent is 0000 0000 0001 0010. This

value indicates that bit B1 and bit B4 are set.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

** > > > > > > > > > > > > > > *

0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

* Least significant bit

** Most significant bit

For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to Status register sets (on page E-

2) and Enable and transition registers

(on page E-18). The individual bits of this register have the following

meanings:

Keithley 2651A Reference Manual

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