Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
RFL DS-562NC RFL Electronics Inc.
July 5, 2012 47 (973)
334-3100
THEORY OF OPERATION
The following is the basic circuit description of the RFL DS-562NC. A simplified block diagram of the module
is shown in Figure 15.
INTRODUCTION
The DS-562NC module provides the following six m
ajor functions: T1/E1 transmit interface, T1/E1 receive
interface, loopback, SCB interfacing, PLL interfacing, and I/O Adapter interfacing. The Actel ProASIC APA-
150 and its associated circuitry
handle all T1/E1 com
m
unication engines, Interface communication engines, and
SCB of the IMUX 2000.
The Xilinx XC9572XL provides buffering between the Actel and the IMUX m
o
therboard signals.
The EXAR XRT8001 IC devices are PLL with frequency synthesizers to provide interface clocks sy
nchronous
to the T1/E1 bus clocks. Other miscellaneous circuits are present to handle the rem
aining functions. A bank of
dip switches is provided to select the module parameters, a toggle switch is provided to select the loopback
function, and LEDs provide the user with module status.
SIGNAL BUFFERING CPLD
The Signal Buffering CPLD consists of a Xilinx XC9572XL which is used to buffer the signals that pass
between the Actel and the IMUX motherboard. These signals include the T1/E1 bus signals and the pass-thru
signals to/from the I/O. It is important to note that the Xilinx is +3V/+5V signal compatible, and therefore
provides the necessary level-translation between the motherboard signals and the Actel which only supports
3.3V signals.
PLL INTEGRATED CIRCUITS
Each PLL IC consists of an EXAR XRT8001 PLL. Each PLL has frequency synthesizers to provide the
necessary 56 Kbps or Nx64 Kbps interface clock that is synchronous to the respective T1/E1 bus clocks. Each
PLL is responsible for one of the two T1/E1 buses, A or B; The FIN input of each PLL is provided with an
8KHZ signal that is synchronous to each of the T1/E1 buses. The Actel FPGA programs each PLL for the
required clock output frequency.
I/O ADAPTER MODULES
The signals to and from the user equipment pass through the I/O module. The I/O module performs the required
level shifting between the DS-562NC and the user equipment, thus allowing the same channel card to be used
with any one of several types of communication interface I/O adapter modules. The supported interface types
include RS-449, RS-530, X.21, V.35, G.703 (Co-Dir & Contra-Dir), RFL Short Haul Fiber, C37.94 (Short-haul
Fiber), and Ethernet (LAN).
COMMS FPGA
The Comms FPGA consists of an Actel ProASIC APA-150 which is the heart of the DS-562NC module. It has
several main functions which include T1/E1 receive and transmit control, SCB interfacing, PLL interfacing, I/O
Interfacing, LED control, reading switch settings, equipment and payload loopback, addressing and CRC, and
I/O type decoding. The Actel also is responsible for programming two external phase locked loops devices.
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