Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
RFL DS-562NC RFL Electronics Inc.
July 5, 2012 48 (973)
334-3100
T1/E1 TRANSMIT CIRCUIT
The 56 or Nx64 Kbps serial data from the user equipment is routed to the transmit circuit which synchronizes
the signals and then feeds them to the T1/E1 data bus. The transmit timeslot utilization is established by using
the starting timeslot, data-rate, and multiplexer type (T1 or E1) information. As multiple timeslots can be used,
a FIFO is used to insure that there is enough data to send onto the T1/E1 bus following circuit initialization;
otherwise data-run out would occur.
The FIFO also synchronizes the data transfer between the interface clock and T1/E1 clock.
If addressing is being used in the 56 Kbps mode, the transm
it address is inserted into the data stream along with
security
coding information.
T1/E1 RECEIVE CIRCUIT
The incoming serial data stream is received from the T1/E1 bus by the receive interface and routed to the user
equipment. The receive timeslot utilization is established by using the starting timeslot, data-rate, and
multiplexer type (T1 or E1) information. A FIFO is used to synchronize the data transfer between the T1/E1
clock and interface clock.
If addressing is being used in the 56 Kbps mode, coded address and security information is extracted and
verified, and then com
pared to the selected received address. The receive data can be optionally squelched if
the 56 Kbps mode when addressing is used but an invalid address is detected.
I/O ADAPTER INTERFACE CIRCUITS
The I/O Adapter Interface circuit is responsible for decoding the Interface I/O Ty
pe installed in the rear slot that
corresponds with the DS-562NC m
odule located in the front slot of the chassis. The state of three ID signals
that pass thru the m
otherboard and the expanded I/O type settings programmed via dip switches or remote SCB
settings are all monitored. The appropriate interface engines are then used based upon the I/O Type installed.
The required data and clocks are also routed as required. The DS-562NC provides clocks to the customer
equipment when a DCE-type I/O Adapter is installed, and receives clocks when a DTE-type I/O Adapter is
installed.
When the RS-449 and the RS-530 I/O adapters are set for DCE, they provide 56 Kbps or Nx64 Kbps TX/RX
clocks that independent of each other, and are relative to the T1 transmit and T1 receive buses respectively
.
The V.35 (DCE) provides 56 Kbps or Nx64 Kbps TX/RX clocks that are in phase with one another and are
based solely
upon the T1/E1 receive bus. The X.21 (DCE
) provides a single clock based solely
upon the T1/E1
receive bus. The incoming data for the V.35 and X.21 (DCE) interfaces must be synchronized to the T1/E1
transmit bus because ONLY the RX clock is used by the interface.
The DTE-type I/O adapters, regardless of RS-449, RS-530, X.21, or V.35, assume that the clocks are not in
phase, but does however require that the clocks provided by
the customer DCE equipment be synchronous to
the multiplexer T1/E1 clocks.
The G.703 Co-Directional I/O adapter is a 64 Kbps DCE interface that generates data with embedded timing
information to the customer equipment based upon the T1 receive clock. The receiver recovers the clock and
data, and then synchronizes the data with the T1 transmitter circuits. Octet timing generation and detection
circuits are used if the Octet timing feature is enabled.
The G.703 Contra-Directional I/O adapter is a 64 Kbps DCE interface that provides TX/RX clocks that
independent of each other, and are relative to the T1 transm
it and T1 receive buses respectively
.
Octet timing
generation circuits are used if the Octet timing feature is enabled.
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