Because RFL™ and Hubbell® have a policy of continuous product improvement, we reserve the right to change designs and specifications without notice.
RFL DS-562NC RFL Electronics Inc.
July 5, 2012 49 (973) 334-3100
The C37.94 Short-haul Fiber I/O adapter’s interface operates in the same fashion as the RS-449 and the RS-530
DCE I/O adapter, the data-rate is provided by signals that originate from the Actel, and ultimately pass thru the
motherboard to the I/O adapter.
The RFL Short-haul Fiber I/O adapter’s interface operates in the same fashion as the RS-449 and the RS-530
DCE I/O adapter, and operates only
at 64 Kbps.
The Ethernet (LAN) adapter’s interface operates in the sam
e fashion as the RS-449 and the RS-530 DCE I/O
adapter. The I/O adapter auto-detects the data-rate, and provides any
data buffering required.
SCB INTERFACE CIRCUIT
The SCB Interface circuit communicates with the CM4 module via the SCB (Serial Control Bus). A DIP switch
is provided to allow the user to set the SCB address of the m
odule which is read by
the SCB FPGA. Each
module installed in the chassis will have a unique SCB address. The DS-562NC module has a type ID of 116
encoded into the SCB FPGA device. The CM-4 module periodically interrogates the DS-562NC to read its
status information. The configuration is also read by the CM-4 if the DS-562NC it is set for “local” mode of
operation, but is written by the CM-4 if set for “remote” mode of operation. A DIP switch is set by the user to
set the DS-562NC for either “local” or “remote” operation.
PLL INTERFACE CIRCUIT
The PLL Interface circuit provides the settings for the EXAR XRT8001 PLL devices. The com
m
unication
between the Actel and PLL is performed serially. The settings are written to the PLL devices, and then they are
read back to verify the settings were correctly written. The state machine continually monitors any requested
change to the PLL parameters. The Actel also provides the FIN input of each PLL with an 8KHZ signal that is
synchronous to each of the T1/E1 buses. The Actel then receives a synthesized clock from each PLL, and routes
them to the T1/E1 circuits and interface I/O circuits, as required.
LOOPBACK CIRCUIT
The T1/E1 transmit and receive interface circuits are interconnected by loopback logic inside the Actel APA-
150. The equipment loopback causes the data received from the user equipment to be read into a buffer and then
retransmitted back to the user equipment. The payload loopback places the T1/E1received data into a buffer and
then retransmits it via the T1/E1 transmit circuit. Synchronizing circuits in the loopback logic compensates for
varying phase relationships between the T1/E1 transmit and receive bus signals. A three position toggle switch
on the module front panel enables the user to select equipment loopback, payload loopback or no loopback.
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