Sel SEL-421 - Example Synchrophasor Protection Free-Form Logic Settings; Example Synchrophasor Port Settings

R.7.30
SEL-421 Relay Reference Manual Date Code 20111215
Synchrophasors
C37.118 Synchrophasor Protocol
The two analog quantities and three Relay Word bits required in this example
must be placed in certain protection math variables and protection SEL
OGIC
variables. Make the Protection Free-Form logic settings in Table 7.18 in all six
settings groups.
Make the Table 7.19 settings for serial port 3, using the SET P 3 command.
The sample MET PM capture in Figure 7.13 shows data that could be
measured by this system, including the digital and analog data near the bottom
of the figure, that represent the protection free-form logic from Table 7.18.
PMID PMU Hardware ID (1–65534) 14
PHDATAV Phasor Data Set, Voltages (V1, ALL, NA) V1
VCOMP Voltage Angle Compensation Factor (–179.99 to 180
degrees)
4.20
PHDATAI Phasor Data Set, Currents (I1, ALL, NA) ALL
PHCURR Current Source (IW, IX, BOTH, COMB) COMB
IWCOMP IW Angle Compensation Factor (–179.99 to 180 degrees) 3.50
IXCOMP IX Angle Compensation Factor (–179.99 to 180 degrees) 5.50
PHNR Phasor Numeric Representation (I = Integer, F = Floating
point)
F
PHFMT Phasor Format (R = Rectangular coordinates, P = Polar
coordinates)
R
FNR Frequency Numeric Representation (I = Integer, F = Float) I
NUMANA Number of Analog Values (0–8) 2
NUMDSW Number of 16-bit Digital Status Words (0, 1, 2) 1
TREA1 Trigger Reason Bit 1 (SEL
OGIC Equation) NA
TREA2 Trigger Reason Bit 2 (SEL
OGIC Equation) NA
TREA3 Trigger Reason Bit 3 (SEL
OGIC Equation) NA
TREA4 Trigger Reason Bit 4 (SEL
OGIC Equation) NA
PMTRIG Trigger (SEL
OGIC Equation) NA
Table 7.18 Example Synchrophasor Protection Free-Form Logic Settings
Setting Value
PSV64 NOT (3PO OR SPO) # Line breaker status
PSV63 LOP # Loss-of-Potential
PMV62 RTD01 # Ambient Temperature
PMV63 DC1 # Station Battery Voltage
Table 7.19 Example Synchrophasor Port Settings
Setting Description Value
PROTO Protocol (SEL, DNP, MBA, MBB, RTD, PMU) PMU
SPEED Data Speed (300 to 57600) 19200
STOPBIT Stop Bits (1, 2 bits) 1
RTSCTS Enable Hardware Handshaking (Y, N) N
FASTOP Enable Fast Operate Messages (Y, N) N
Table 7.17 Example Synchrophasor Global Settings (Sheet 2 of 2)
Setting Description Value