ST STM32WL55JC

Debug support (DBG) RM0453
1322/1454 RM0453 Rev 2
• This data is then shifted while the TAPSM is in the Shift-DR state, in the same manner
as the IR shift in the Shift-IR state.
• When the TAPSM goes through the Update-DR state, the value scanned into the DR
scan chain is transferred into the selected data register.
• When the TAPSM is in the Run-Test/Idle state, no special actions occur. The IDCODE
instruction is loaded in the instruction register.
When active, the nJTRST signal resets the state machine asynchronously to the
Test-Logic-Reset state.
The data registers corresponding to the 4-bit IR instructions are listed in Table 263.
Table 263. JTAG-DP data registers
IR
instruction
Data
register
Scan chain
length
Description
0000 to 0111 (BYPASS) 1 Not implemented: BYPASS selected
1000 ABORT 35
ABORT register
– Bits 34:1 = Reserved
– Bit 0 = APABORT: write 1 to generate an AP abort.
1001 (BYPASS) 1 Reserved: BYPASS selected
1010 DPACC 35
Debug port access register
Initiates the debug port and gives access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register
Bit 0 = RnW = Read request (1) or write request (0)
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data read following a read request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge
010 = OK/FAULT
001 = WAIT
OTHER = reserved
1011 APACC 35
Access port access register
Initiates an access port and gives access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit sub-address of an access port register
Bit 0 = RnW= Read request (1) or write request (0)
– When transferring data OUT:
Bits 34:3 = DATA[31:0] = 32-bit data read following a read request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge
010 = OK/FAULT
001 = WAIT
OTHER = reserved
1100 (BYPASS) 1 Reserved: BYPASS selected
1101 (BYPASS) 1 Reserved: BYPASS selected