Debug support (DBG) RM0453
1404/1454 RM0453 Rev 2
38.11.7 TPIU formatter synchronization counter register (TPIU_FSCR)
Address offset: 0x308
Reset value: 0x0000 0040
38.11.8 TPIU claim tag set register (TPIU_CLAIMSETR)
Address offset: 0xFA0
Reset value: 0x0000 000F
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. CYCCOUNT[12:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bits 12:0 CYCCOUNT[12:0]: enables effective use of different sized TPAs without wasting large
amounts of the storage capacity of the capture device
This counter contains the number of formatter frames since the last synchronization packet of
128 bits. It is a 12-bit counter with a maximum count value of 4096. This equates to
synchronization every 65536 bytes, that is, 4096 packets x 16 bytes per packet. The default
is set up for a synchronization packet every 1024 bytes, that is, every 64 formatter frames. If
the formatter is configured for continuous mode, full and half-word sync frames are inserted
during normal operation. Under these circumstances, the count value is the maximum
number of complete frames between full synchronization packets.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMSET[3:0]
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMSET[3:0]: sets claim tag bits
Write:
0000: No effect
xxx1: Sets bit 0.
xx1x: Sets bit 1.
x1xx: Sets bit 2.
1xxx: Sets bit 3.
Read:
0xF: Indicates there are four bits in claim tag.
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