RM0453 Rev 2 405/1454
RM0453 General-purpose I/Os (GPIO)
426
10.4.6 GPIOx output data register (GPIOx_ODR) (x = A to B)
Address offset: Block A: 0x0014
Address offset: Block B: 0x0414
Reset value: 0x0000 0000
10.4.7 GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B)
Address offset: Block A: 0x0018
Address offset: Block B: 0x0418
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OD[15:0]: Port Px[15:0] output data
These bits can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR and GPIOx_BRR registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109876543210
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 BR[15:0]: Port Px[15:0] reset output data bit [15:0] in GPIOx_ODR
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)
1: Resets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).
Note: If both BSy and BRy are set, BSy has priority.
Bits 15:0 BS[15:0]: Port Px[15:0] set output data bit [15:0] in GPIOx_ODR
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)
1: Sets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).
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