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General-purpose I/Os (GPIO) RM0453

406/1454 RM0453 Rev 2

10.4.8 GPIOx configuration lock register (GPIOx_LCKR) (x = A to B)

Address offset: Block A: 0x001C

Address offset: Block B: 0x041C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence

is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the

GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the lock

sequence has been applied on a port bit, the value of this port bit can no longer be modified

until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to GPIOx_LCKR . Only word access (32-bit long)

is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function

registers).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU

reset or peripheral reset.

LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

RD LCKR

RD LCKR[16] = 1 (This read operation is optional but it confirms that the lock is active.)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit

returns 1 until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port Px[15:0] lock configuration

These bits are read/write but can only be written when the LCKK bit is 0.

0: Port Pxy configuration not locked (y = 0 to 15)

1: Port Pxy configuration locked (y = 0 to 15)

ST STM32WL55JC User Manual

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