Extended interrupts and event controller (EXTI) RM0453
518/1454 RM0453 Rev 2
16.6.7 EXTI software interrupt event register (EXTI_SWIER2)
Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.
16.6.8 EXTI pending register (EXTI_PR2)
Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. SWI45 Res. Res. Res. SWI41 SWI40 Res. Res. Res. Res. Res. SWI34 Res. Res.
rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 SWI45: software interrupt on event 45
A software interrupt is generated independently from the setting in EXTI_RTSR and
EXTI_FTSR. This bit always returns 0 when read.
0: Writing 0 has no effect.
1: Writing 1 to this bit triggers an event on line 45.
This bit is automatically cleared by hardware.
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 SWI41: software interrupt on event 41
Bit 8 SWI40: software interrupt on event 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 SWI34: software interrupt on event 34
Bits 1:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. PIF45 Res. Res. Res. PIF41 PIF40 Res. Res. Res. Res. Res. PIF34 Res. Res.
rw rw rw rw
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