RM0453 Rev 2 519/1454
RM0453 Extended interrupts and event controller (EXTI)
523
16.6.9 EXTI interrupt mask register (EXTI_CnIMR1)
Address offset: Block 1: 0x080
Address offset: Block 2: 0x0C0
Reset value: 0x0000 0000
16.6.10 EXTI event mask register (EXTI_CnEMR1)
Address offset: Block 1: 0x084
Address offset: Block 2: 0x0C4
Reset value: 0x0000 0000
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 PIF41: pending bit on event input 41
Bit 8 PIF40: pending bit on event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM[31:16]
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1514131211109876543210
IM[15:0]
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Bits 31:0 IM[31:0]: wakeup with interrupt mask on event input x (x= 31 to 0)
For each bit of this field:
0: Wakeup with interrupt request from line x is masked.
1: Wakeup with Interrupt request from line x is unmasked.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. EM22 EM21 EM20 EM19 EM18 EM17 Res.
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1514131211109876543210
EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0
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