3.8.3 Circuit Explanation
(1) CPU (U201)
The TMP68301AF-16 (TOSHIBA) is used as the Central Processing Unit (CPU) with the clock
frequency of 16 MHz. This CPU includes the 68HC000 as a core, SIO, PIO, CTC, Interrupt
Controller, Address Decoder, CGC, etc.
(2) Clock Frequency Generator Circuit (X201, U212, 213, 320)
The following clock frequencies are generated, divided from the 32 MHz oscillator.
• 16 MHz (CPU Clock)
• 16 MHz (Clock for Motor Controller)
• 8 MHz (for LCD Controller and Standard CLK for driving ID Unit Motor)
• 4 MHz (CPU Clock for controlling temperature)
• 2 MHz (for LCD Controller)
• 500 KHz (Clock for Motor Controller)
4.91 MHz is used for each CLK of two A/D Converters respectively.
(3) Interrupt Controller (U201, 202, 209)
This function is performed by using the interrupting function built in the CPU and the interrupt
controller. The interrupt controller is used, extended from INT2 of the CPU. When the CPU receives
‘INT’, it proceeds in accordance with the prescribed priority of the program.
(4) Voltage Drop Monitor Circuit (U507, 508)
When the Power Source of 24 V decreases to approximately 20.7 V and the PS of 15 V to 13.8 V
respectively, this circuit can detect the voltage decrease by interrupt signal and latch.
(5) RESET, Backed-up Switching Circuit (U210, U804)
This circuit monitors the digital 5 V source, and if it becomes less than approximately 4.75 V, RESET
signal is generated and the protection for writing of the backed-up RAM and real time clock is
performed at the same time. Also the DC + 5 V is switched by the battery power source. This circuit
generates “L” when the voltage becomes less than 4 V to avoid unstable RESET signal.
(6) EEPROM, WORK RAM, B. B. RAM (EEPROM: U905 WORK RAM: U901 ~ 904 B. B. RAM:U801,
802)
EEPROM is 8KB, WORK RAM is 512 KB with SRAM, and B. B. RAM (Battery Backed-up RAM) is
256 KB with SRAM.
(7) Real Time Clock (U803)
This is battery backed-up as the calendar clock.
(8) PRCN1 Interface (U301, 312, 313)
This circuit performs the interface with the control board (PCB No. 6350 PRCN1) for Built-In Printer. It
uses a port (U301) and buffers (U312, 313).
(9) LCD Interface (U701, 702, 704)
This circuit performs the LCD display by using the LCDC (LCD Controller (U701)). It writes the
display dot image on the 256Kbit VRAM (U705) by the LCDC, and displays on the LCD via the buffer
(U702) based on the image data. 8 MHz frequency is supplied as the internal clock and 2 MHz is
supplied for LCD display timing.
The negative voltage of the LCD drive is created from + 5 V by the DC-DC Converter (U704).
For the contrast signal, the voltage divided from the above negative voltage by the external volume
PCB No. 9263 (VR) is supplied to LCD.
CA-500 Series S/M 3-18 Revised December 2001 8
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