GR712RC-UM, Jun 2017, Version 2.9 17 www.cobham.com/gaisler
GR712RC
1.7.11 Technical Note on LEON SRMMU Behaviour
The MMU behavior when updating the FSR and FAR registers in this device does not fully comply to
the SPARC V8 Manual. Special care should be taken by users that utilize the MMU. This is addressed
in Linux release 3.10.58-1.0.4 and onwards. Other users who implement MMU handling should con-
sult [MMU] for further information.
1.7.12 Technical Note on GRETH Ethernet Controller Behaviour
The state in which the GRETH receiver control finite state machine discards packets does not take
overrun into account in all cases. The discard state is entered when a received packet is determined to
be dropped. The size of the packet is checked and that amount of data is read from the FIFO. When an
overrun has occurred, the amount written to the FIFO is not the same as the length of the packet and in
those cases the FIFO should be emptied completely. This was not done if:
1 The packet in question had a MAC address which the core should not receive, or
2 if the receiver was enabled when the packet was received but the descriptor was not enabled and the
descriptor read was so slow that an overrun occurred during that time.
These conditions cause the Ethernet receiver to hang. No further traffic can be received and the
GRETH must receive a hardware reset to recover. This hardware reset can be attained by either reset-
ing the whole device or, in devices that have individual clock gating of the Ethernet controller, forcing
a reset of the GRETH via the system's clock gating unit.
Workaround
As described in the previous section, the problem occurs under two conditions. The first condition can
be avoided by enabling promiscuous mode for the Ethernet controller. This mode is enabled via the
GRETH control register. Promiscuous mode may lead to additional software load of the systems since
more packets may need to be processed. In applications where the GRETH is used in a limited net-
work with few members, the addition of promiscuous mode should have less negative effects.
Use of switches instead of hubs in the network since the GRETH controller will in this case receive
fewer packets with MAC addresses that will be discarded.
The second trigger condition is system and application specific. The condition is not expected to hap-
pen in systems like the affected components listed earlier in this document. Other systems with mem-
ory controllers that have high latency and systems that introduce several bridges between the GRETH
controller and main memory may encounter condition 2.
There is no status bit in the controller that will indicate that the receiver has hanged. The condition
can be detected by the Ethernet controller no longer receiving any packets. This could require imple-
mentation at a higher level of a heart beat function so that system software can detect that packets are
missing and correct the situation. The only way to correct the condition is to perform a hardware reset
of the GRETH controller. The soft reset functionality that can be triggered via the GRETH control
register is not enough to resolve the receiver hang.
Users of the GRETH Ethernet Controller should consult [GRETH] for further information and
updates.
1.7.13 Technical Note on Stale Cache Entry After Store with Data Tag Parity Error
Under certain conditions, a data coherency issue can occur when the processor has executed a back-
to-back store operation and the first store's address hits a cache set that has a data cache tag parity
error. The second store operation successfully stores its data content into the main memory but the
data cache controller fails to update the old data in the data cache with the new data from the store
operation. This leads to an incoherent state, data in the data cache is not the same as in the main mem-
ory. A subsequent read from the second location will get the old data instead of the new data if the
data cache line is still valid in the cache.
Refer to [B2B] for further details and workaround.
1.7.14 Never disable the TLB when the MMU is enabled
When the MMU is enabled but TLB disabled, the MMU can in certain cases perform incorrect
address translation. Therefore it is advised to never set the TLB disable bit in the MMU control regis-
ter. The TLB disable bit is not set by any operating system provided by Cobham Gaisler.
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