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R.A.76

SEL-421 Relay Reference Manual Date Code 20111215

Relay Word Bits

Row List

274 LPSEC Direction of the upcoming leap second. During the time that

LPSECP is asserted, if LPSEC is asserted, the upcoming

leap second is deleted; otherwise, the leap second is added.

274 LPSECP Leap second pending

274 TQUAL8 Time quality, binary, add 8 when asserted

274 TQUAL4 Time quality, binary, add 4 when asserted

274 TQUAL2 Time quality, binary, add 2 when asserted

274 TQUAL1 Time quality, binary, add 1 when asserted

275 * Reserved

These Relay Word bits are valid when an IRIG-B timekeeping source is connected that

includes the IEEE C37.118 IRIG-B control bits in the data stream. Otherwise, these Relay Word

bits are indeterminate. When the SEL-421 is not connected to an IRIG source, these Relay

Word bits are deasserted, except for TQUAL8–TQUAL1, which are asserted.

The SEL-421 uses the year information obtained from IRIG-B to set the internal clock year

value if EPMU := Y.

See IRIG-B on page U.4.71.

Table A.51 Time-Error Calculation (Sheet 1 of 2)

Row Bit Name Description

276 LOADTE Load TECORR Factor (SELOGIC Equation). When a

rising-edge is detected, the accumulated time-error value

TE is loaded with the TECORR factor (preload value).

276 STALLTE Stall Time-Error Calculation (SELOGIC Equation). When

asserted, the time-error calculation is stalled, or frozen.

276 PLDTE Asserts for approximately 1.5 cycles when the TEC com-

mand is used to load a new time-error correction factor

(preload value) into the TECORR analog quantity.

276 * Reserved

277 * Reserved

Table A.50 Time and Synchronization Control Bits

(Sheet 2 of 2)

Row Bit Name Description

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