RM0453 Rev 2 889/1454
RM0453 General-purpose timer (TIM2)
893
26.4.21 TIM2 DMA address for full transfer (TIM2_DMAR)
Address offset: 0x4C
Reset value: 0x0000
26.4.22 TIM2 option register 1 (TIM2_OR1)
Address offset: 0x50
Reset value: 0x0000 0000
26.4.23 TIM2 alternate function option register 1 (TIM2_AF1)
Address offset: 0x60
Reset value: 0x0000 0000
1514131211109876543210
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP[1:0]
ETR_
RMP
Res.
rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:2 TI4_RMP[1:0]: Timer input 4 remap
Set and cleared by software.
00: TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping
01: TIM2 TI4 is connected to COMP1_OUT
10: TIM2 TI4 is connected to COMP2_OUT
11: TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT
Bit 1 ETR_RMP: External trigger 1 remap
Set and cleared by software.
0: TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping
1: LSE internal clock is connected to TIM2_ETR input
Bit 0 Reserved, must be kept at reset value.
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