ABB RED650 - Page 268

U1>
U
a>b
a
b
t
tReset1
t
t1
AND
TR1
ST1
OFF
Delay
ON
Delay
IEC10000100-2-en.vsd
IEC10000100 V2 EN-US
Figure 122: Logic diagram for step 1, Definite time delay, DT operation
U1<
ST1
TR1
tReset1
t1
IEC10000039-3-en.vsd
IEC10000039 V3 EN-US
Figure 123: Example for Definite Time Delay stage 1 reset
Section 9 1MRK 505 394-UEN A
Voltage protection
262 Line differential protection RED650 2.2 IEC
Technical manual