ABB RED650 - Time Sequence Diagrams

IEC16000160-1-en.vsdx
Priority
AND
OR
High (Master)
inProgress
unsuccessful
WFMASTER
Master:
Slave:
Priority
Low (Slave)
AND
AND
start
WAIT
t
tWaitForMaster
AND
AND
S
R
OR
inhibit
commandCloseCB
reclaimTimeStarted
inhibitWaitForMaster
slaveDeadTime
wait
IEC16000160 V1 EN-US
Figure 159: Master-Slave
If reclosing of the first circuit breaker is unsuccessful, the UNSUCCL output
connected to the INHIBIT input of the slave unit interrupts the reclosing sequence
of the latter. The signals can be cross-connected to allow simple changing of the
priority by just setting the High and the Low priorities without changing the
configuration. The CBCLOSED inputs from each circuit breaker are important in
multi-breaker arrangements to ensure that the circuit breaker was closed at the
beginning of the sequence. If the High priority breaker was not closed its auto
reclosing sequence will not start and the low priority breaker will just continue its
auto reclosing sequence in accordance with its normal settings.
12.2.6.5 Time sequence diagrams
M12458-10 v5
Some examples of the timing of internal and external signals at typical transient
and permanent faults are shown below in Figure
160 to 163.
Section 12 1MRK 505 394-UEN A
Control
342 Line differential protection RED650 2.2 IEC
Technical manual