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Agilent Technologies n5181a - Questionable:frequency:condition; Questionable:frequency:enable; Questionable:frequency:ntransition; Questionable:frequency:ptransition

Agilent Technologies n5181a
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96 Agilent N5181A/82A MXG Signal Generators SCPI Command Reference
System Commands
Status Subsystem (:STATus)
:QUEStionable:FREQuency:CONDition
Supported All
:STATus:QUEStionable:FREQuency:CONDition?
This query returns the decimal sum of the bits in the Data Questionable Frequency Condition
Register. For example, if the 1 GHz internal reference clock is unlocked (bit 2), a value of 4 is
returned.
Range 0–32767
Remarks The data in this register is continuously updated and reflects current conditions.
Refer to the Programming Guide for more information.
:QUEStionable:FREQuency:ENABle
Supported All
:STATus:QUEStionable:FREQuency:ENABle <value>
:STATus:QUEStionable:FREQuency:ENABle?
This command determines which bits in the Data Questionable Frequency Event Register will set the
frequency summary bit (bit 5) in the Data Questionable Condition Register.
The variable <value> is the sum of the decimal values of the bits that you want to enable.
Range 0–32767
Remarks Refer to the Programming Guide for more information.
:QUEStionable:FREQuency:NTRansition
Supported All
:STATus:QUEStionable:FREQuency:NTRansition <value>
:STATus:QUEStionable:FREQuency:NTRansition?
This command determines which bits in the Data Questionable Frequency Condition Register will set
the corresponding bit in the Data Questionable Frequency Event Register when that bit has a
negative transition (1 to 0).
The variable <value> is the sum of the decimal values of the bits that you want to enable.
Range 0–32767
Remarks Refer to the Programming Guide for more information.
:QUEStionable:FREQuency:PTRansition
Supported All
:STATus:QUEStionable:FREQuency:PTRansition <value>
:STATus:QUEStionable:FREQuency:PTRansition?
This command determines which bits in the Data Questionable Frequency Condition Register will set
the corresponding bit in the Data Questionable Frequency Event Register when that bit has a positive
transition (0 to 1).

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