Chapter 5 How to Operate BERT
5-28.
5.3 Setting Restrictions
The setting items of the PPG have the following restrictions.
When Test Pattern is not PRBS (Test Pattern is 1/2 Clock or 1/16 Clock) in
MP2110A, the Pattern Sync is disabled due to the hardware restrictions.
The setting item can be selected, but “PPG 1/8 Clock” is output under this
condition.
When the following conditions are met, no signal is output from Clk Out.
The bit rate operates in the range from 24.3 to 28.2 Gbit/s.
“1/2 Clock Pattern” is set at PPG Test Pattern in one of the channels
specified at the Clk Out Source Channel setting (Ch1/2 or Ch3/4).
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