Cisco D9854 User Manual

4021470 Rev D D9854 Advanced Program Receiver Installation and Operation Guide 6-21
Memory Usage
Secondary
Set Excessive (stack/
partition) memory
usage
Cause: Possible software
issue.
Remedy: Clear warnings,
reset the unit, and notify
customer service if the
problem persists.
Software exceeding
allowable memory
usage.
Clear Normal (stack/
partition) memory
usage
FPGA Code Version Set FPGA newer than
SW,
Supported=%02u.%0
2u.%02u.%02u,
Running=%02u.%02u
.%02u.%02u
Cause: FPGA version is
newer than the software
can support.
Remedy: Clear warnings,
reset the unit, and notify
customer service if the
problem persists.
Software indicates
FPGA version is
newer than it can
support.
Clear FPGA code ver OK
Ethernet PHY n Set Link is down. Cause: No ethernet cable
connected, faulty cabling,
multiple devices sharing
MAC address on same IP
segment, or possible HW
issue.
Remedy: Check cabling,
check MAC addresses,
clear warnings, reset the
unit, and notify customer
service if the problem
persists.
Ethernet MAC PHY
device is attempting
to reconnect to
external devices.
Clear Connection OK
FW: Resource Use
Host
Set Memory or List Near
Full
Cause: Possible software
issue.
Remedy: Clear warnings,
reset the unit, and notify
customer service if the
problem persists.
Software exceeding
allowable usage of
internal constructs.
Clear Normal Level
FW: Resource Use
Second
Set Memory or List Near
Full
Cause: Possible software
issue.
Remedy: Clear warnings,
reset the unit, and notify
customer service if the
problem persists.
Software exceeding
allowable usage of
internal constructs.
Clear Normal Level
Warning Message
Type
Message Cause/Remedy Description

Cisco D9854 Specifications

General

Model	D9854
Category	Receiver
Output	ASI, IP
Decoding	MPEG-2
Conditional Access	BISS
Receiver Type	Professional IRD
解密	DVB-CSA, BISS, AES
Input Frequency Range	950 MHz to 2150 MHz
Modulation Formats	QPSK, 8PSK
Symbol Rate	1 to 45 Msps
Power Supply	100-240 VAC, 50/60 Hz
Power Consumption	40W (typical)
Operating Temperature	0°C