COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 14 www.cobham.com/gaisler
GR712RC
Note: MKPROM2 currently does not support generation of EDAC checkbytes for more than one
PROM bank.
1.7.8 LEON3FT Cache Controller: Incorrect Bus Access After Power-Down
A LEON with support for clock gating has one clock that is kept running and one clock that is gated
off in power-down mode. Due to a design error, the gated clock was used for logic that keeps track of
the state of the AMBA bus. Due to this error, the first instruction or data (whichever is first) access to
the bus after leaving power-down might be performed incorrectly.
The errata triggers a failure when all of the following conditions are met:
• The processor enters power-down mode while it has received grant to the bus
• For data cache: The instructions to be executed after the power-down instruction contain a load or
store instruction. The memory position accessed is not present in the data cache, or is located in a
noncachable memory area.
For instruction cache: The instructions following the power-down instruction are not present in the
instruction cache or the instruction cache is disabled.
• The processor leaves power-down mode and has lost grant to the bus. For this condition to be met,
another master in the system has made a bus access simultaneously with the processor leaving power-
down mode.
The default behaviour in GRLIB systems is to grant master 0 by default, this master is typically the
LEON processor.
On systems where the errata is applicable and not using any of the workarounds described in this doc-
ument, the impact is that:
• The first data access that goes to the AHB bus may not be performed correctly. If it was a load it will
return invalid data.
• If the instruction cache is disabled, or if the processor is executing from a memory area marked as
noncachable, then the instruction fetch when the processor leaves power-down mode may return
erroneous data that will be interpreted as an instruction and executed by the processor.
Workaround 1: Do not use power-down
The issues described in this document are avoided by not entering power-down mode. Refrain from
using the wr %asr19 sequence.
Workaround 2: Keep instruction cache enabled, execute power-down sequence from cacheable
memory.
When executing from cacheable memory with the instruction cache enabled, the sequence below is
immune to the errata and is suitable for systems that have been implemented with a MMU:
unsigned int address = (unsigned int)<any physical memory address>;
__asm__ __volatile__ (
"mov %%g0, %%asr19\n"
"lda [%0] 0x1C, %%g0\n"
:
: "r"(address));
The power-down sequence that makes use of ASI 0x1C will only work on systems that have been
implemented with a MMU. For systems without MMU, a noncacheable APB register can be used as
source for the load:
unsigned int address = (unsigned int)<address of noncacheable memory. like APB, PnP>;
__asm__ __volatile__ (
"mov %%g0, %%asr19\n"
"ld [%0], %%g0\n"
:
: "r"(address));
Note that the stack pointer or other cachable memory should never be used as the source operand,
even if using ASI 1, since this may lead to faulty data being loaded into the data cache. Also note that

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English