GR712RC-UM, Jun 2017, Version 2.9 15 www.cobham.com/gaisler
GR712RC
FIFOs should not be accessed via the LD. The recommended address to use for the load in both cases
above is the AMBA plug&play area, typically at top of RAM (address 0xFFFFFFF0) 1 .
The load instruction after the write to %asr19 provides immunity against a data cache failure due to
the error described by this errata. After coming back from power-down with a pending interrupt, the
instruction following the %asr19 access will be executed prior to taking the interrupt trap. The load
will be executed on the bus before trying to fetch the first instruction of the trap handler. So even if the
trap handler is not currently in cache, the load will occur before fetching it. The load will also be exe-
cuted to memory before trying to fetch any instruction from the calling function.
Both the write to asr19 and the load, plus the three following instructions, are guaranteed to be in the
I-cache when leaving power-down since they are the last to be fetched into the pipeline before enter-
ing power-down.
Software packages with workarounds
The Cobham Gaisler provided run time environments, from versions shown below, have integrated a
workaround for the data cache for this bug. The software is assumed to be run with cache enabled
(default behaviour in bootladers) and from cacheable memory and does not include any workaround
for the instruction cache, since this is not required with these assumptions.
1.7.9 Failing SDRAM Access After Uncorrectable EDAC Error
When the memory controller of the GR712RC LEON system detects an uncorrectable EDAC error, it
should respond with an AMBA ERROR response and then return to normal operation. Due to an
incomplete condition check for starting new SDRAM accesses, the memory controller may perform a
read access following an uncorrectable error even if there is no incoming access on the AMBA bus.
The result will be discarded unless a AMBA read access to the SDRAM memory area is performed
before the SDRAM read operation has finished. The extra read access will not occur if there is a
SDRAM refresh operation pending.
The memory controller will return to normal operation after the extra read access has been performed.
If a AMBA read is performed to the SDRAM area before this unintended read access has completed
then the result of the incoming AMBA read access may be erroneous. The result can be an AMBA
ERROR response or the memory controller may deliver data from the wrong memory location with-
out a AMBA ERROR response (note that the first access that read a location which had an uncorrect-
able error will always receive an AMBA ERROR response).
The erratum can be triggered when:
• The FTMCTRL has been configured with minimum t
RP
SDRAM timing, and
• A read access to SDRAM results in an uncorrectable EDAC error, and
• A second AMBA read access is performed to the SDRAM memory area in the window zero to five
system clock cycles after the AMBA ERROR response given due to the uncorrectable EDAC error.
If the incoming read access occurs during the last cycle of the vulnerable window in time then the
controller will return data from the memory location of the first access, which will may trigger an
AMBA ERROR response if the uncorrectable error remains at that memory location. For incoming
accesses during the other cycles in the vulnerable window, the access will malfunction but the data
read by the memory controller may still have valid check bits. If the check bits are valid then the erro-
neous data will be delivered without any AMBA ERROR for the second access.
BCC (bare-C) Not applicable, does not use power-down instruction
Linux 2.6.21 (SnapGear p42)
All 2.6.36 releases and later that have been distributed via
Cobham Gaisler
In mainline since 2.6.39
RCC (RTEMS) RCC-1.2.x based on RTEMS-4.10 and later
VxWorks VxWorks 6.3 and 6.5 are not affected since power-down is not
used
Fixed in 6.7 since release 1.0.3
To Next Page
Loading...
Need help?
General
