COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 169 www.cobham.com/gaisler
GR712RC
30 Loop mode (LOOP) - When this bit is set, and the core is enabled, the core’s transmitter and receiver
are interconnected and the core will operate in loopback mode. The core will still detect, and will be
disabled, on Multiple-master errors.
29 Clock polarity (CPOL) - Determines the polarity (idle state) of the SPICLK clock.
28 Clock phase (CPHA) - When CPHA is ‘0’ data will be read on the first transition of SPICLK. When
CPHA is ‘1’ data will be read on the second transition of SPICLK.
27 Divide by 16 (DIV16) - Divide system clock by 16, see description of PM field below and see sec-
tion 23.2.3 on clock generation. This bit has no significance in slave mode.
26 Reverse data (REV) - When this bit is ‘0’ data is transmitted LSB first, when this bit is ‘1’ data is
transmitted MSB first. This bit affects the layout of the transmit and receive registers.
25 Master/Slave (MS) - When this bit is set to ‘1’ the core will act as a master, when this bit is set to ‘0’
the core will operate in slave mode. This implementation only supports operation in master mode.
Software must set this bit to ‘1’.
24 Enable core (EN) - When this bit is set to ‘1’ the core is enabled. No fields in the mode register
should be changed while the core is enabled. This can bit can be set to ‘0’ by software, or by the core
if a multiple-master error occurs.
23: 20 Word length (LEN) - The value of this field determines the length in bits of a transfer on the SPI bus.
Values are interpreted as:
0b0000 - 32-bit word length
0b0001-0b0010 - Illegal values
0b0011-0b1111 - Word length is LEN+1, allows words of length 4-16 bits.
19: 16 Prescale modulus (PM) - This value is used in master mode to divide the system clock and generate
the SPI SPICLK clock. The value in this field depends on the value of the FACT bit.
If bit 13 (FACT) is ‘0’:The system clock is divided by 4*(PM+1) if the DIV16 field is ‘0’ and
16*4*(PM+1) if the DIV16 field is set to ‘1’. The highest SPICLK frequency is attained when PM is
set to 0b0000 and DIV16 to ‘0’, this configuration will give a SPICLK frequency that is (system
clock)/4. With this setting the core is compatible with the SPI register interface found in MPC83xx
SoCs.
If bit 13 (FACT) is ‘1’: The system clock is divided by 2*(PM+1) if the DIV16 field is ‘0’ and
16*2*(PM+1) if the DIV16 field is set to ‘1’. The highest SPICLK frequency is attained when PM is
set to 0b0000 and DIV16 to ‘0’, this configuration will give a SPICLK frequency that is (system
clock)/2.
15:14 RESERVED
13 PM factor (FACT) - If this bit is 1 the core’s register interface is no longer compatible with the
MPC83xx register interface. The value of this bit affects how the PM field is utilized to scale the SPI
clock. See the description of the PM field.
12 RESERVED
11: 7 Clock gap (CG) - The value of this field is only significant in master mode. The core will insert CG
SPICLK clock cycles between each consecutive word. This only ap
plies when the transmit queue is
kept non-empty. After the last word of the transmit queue has been sent the core will go into an idle
state and will continue to transmit data as soon as a new word is written to the transmit register,
regardless of the value in CG. A value of 0b00000 in this field enables back-to-back transfers.
6: 0 RESERVED (R) - Read as zero and should be written as zero to ensure forward compatibility.
Table 175. SPI controller Event register
31 30 15 14 13 12 11 10 9 8 7 0
TIP R LT ROVUNRNENF R
31 Transfer in progress (TIP) - This bit is ‘1’ when the core has a transfer in progress. Writes have no
effect.
30: 15 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
14 Last character (LT) - This bit is set when a transfer completes if the transmit queue is empty and the
LST bit in the Command register has been written. This bit is cleared by writing ‘1’, writes of ‘0’
have no effect.
13 RESERVED (R) - Read as zero and should be written to zero to ensure forward compatibility.
Table 174. SPI controller Mode register

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English