GR712RC-UM, Jun 2017, Version 2.9 176 www.cobham.com/gaisler
GR712RC
20:16 Clock Scale HIGH (CLKSCALEH) - This value determines how many system clock cycles the
SCLK clock is high. The SCLK clock’s high time is CLKSCALEH+1 system clock cycles. Please
see section 24.2.6 for a description of clock scaling.
15:5 RESERVED
4:0 Clock scale LOW (CLKSCALEL) - This value determines how many system clock cycles the SCLK
clock is low. The SCLK clock’s low time is CLKSCALEL+1 system clock cycles. Please see section
24.2.6 for a description of clock scaling.
Reset value: 0x00000000
Table 187. GRSLINK Control register
31 30 29 26 25 16
ODEL RESERVED SLEN
15 987 43210
RESERVED SRO SCN PAR AS SE SLE
31:30 Output delay (ODEL) - This field determines the delay applied to transitions on the SDO and SYNC
lines relative to the SLINK clock SCLK. The SDO and SYNC signals will transition ODEL+1 sys-
tem clock cycles after the rising edge on SCLK. This means that the delay can be adjusted between 1
and 4 system clock cycles.
29:26 RESERVED
25:16 SEQUENCE Length (SLEN) - Number of elements in a SEQUENCE. The value is encoded as num-
ber of elements - 1; when this field is set to 0 the core will perform one operation from the A array.
Or, if the SRO bit is set, only transfer one element to the B array.
15:9 RESERVED
8 SEQUENCE Receive Only (SRO) - When this bit is set the core will not transmit any words as part
of a SEQUENCE operation. The core will only access the B array.
7:4 SEQUENCE Channel Number (SCN) - When the SLINK core is performing a SEQUENCE of oper-
ations it compares the channel number in the incoming packets with the value of this field to deter-
mine if the received word is a response to a SEQUENCE operation.
3 Parity (PAR) - This bit determines the method used to calculate the parity bit in the SLINK data
words. When this bit is set to ‘1’ the core uses odd parity, when the bit is set to ‘0’ the core uses even
parity. The core reads the value of this bit during each SYNC cycle, however the bit’s value should
only be changed when the core is disabled. Default value: ‘1’ - odd parity.
2 Abort SEQUENCE (AS) - Setting this bit aborts an ongoing SEQUENCE. This bit is automatically
cleared when the SEQUENCE has stopped.
1 SEQUENCE Enable (SE) - When this bit is set to ‘1’ the core will use the Array base addresses to
perform a SEQUENCE of SLEN operations. This bit is automatically cleared by the core after the
SEQUENCE has completed and can not be reset by writes to this register.
0 SLINK Enable (SLE) - When this bit is set the core will accept transmit requests and react to incom-
ing data on the bus. When this bit is ‘0’ the controller will not generate the SCLK clock and SYNC
pulses and will not perform, or react to, any communication on the bus.
When the core is enabled it always outputs one NULL word before issuing the first SYNC pulse.
When the core is disabled by writing ‘0’ to this bit, the SCLK clock stops within one SCLK period.
Reset value: 0x00000008
Table 188. GRSLINK NULL word register
31 24 23 0
RESERVED NULLWORD
31:24 RESERVED
Table 186. GRSLINK Clock Scaler register
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