COBHAM GR712RC - Page 55

GR712RC-UM, Jun 2017, Version 2.9 55 www.cobham.com/gaisler
GR712RC
Figure 18. Prom read access with two waitstates.
data1 data2
address
romsn
data
oen
cb
data2data lead-out
sdclk
A1
D1
CB1
data2
Figure 19. Prom write cycle (0-waitstates)
data
address
romsn
data
writen
cb
lead-out
sdclk
A1
D1
CB1
lead-in
Figure 20. Prom write cycle (2-waitstates)
data
address
romsn
data
writen
cb
lead-out
sdclk
A1
D1
CB1
lead-in data
data