AH500 Module Manual
10-16
Note: D1000 and D500 in the above window are the registers in an AH500 series CPU module on
the left of AH10DNET-5A functioning as a slave.
The following figure illustrates the corresponding relations in the mapping areas of the master and
slave. The master and slave both consist of AH10DNET-5A and an AH500 series CPU module.
DeviceNet
(AH500 + AH10DNET-5A)
Slave
D505~
D999
D1005~
D1499
(AH500 + AH10DNET-5A)
Master
D500~
D999
D1000~
D1499
Note: In the above figure, the maximum data length is introduced. But the actually configured data
length may be different from it.
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