GW Instek GDM-906 Series - Page 322

GDM-906X Series User Manual
322
STATus:QUEStionable:CONDition?
Returns the contents of the Questionable Condition register.
Return parameter: <NR1>, Ex: +2
●A condition register continuously monitors the state of the instrument.
Condition register bits are updated in real time; they are neither latched nor
buffered.
●This register is read-only; bits are not cleared when read.
STATus:QUEStionable:ENABle
Set bits in the Ouesrionable Enable register.
Parameter: <NR1> (0~32767)
Example: STAT:QUES:ENAB 4099
Sets the bit0, bit1 and bit12 in Ouesrionable Enable register, 4099 = 2
0
+ 2
1
+ 2
12
.
●The selected bits are then reported to the Status Byte. An enable register
defines which bits in the event register will be reported to the Status Byte
register group. You can write to or read from an enable register.
●A STATus:PRESet clears all bits in the enable register.
●The *PSC command controls whether the enable register is cleared at
power on.
STATus:QUEStionable:ENABle?
Returns the total number of the Ouesrionable Enable register.
Return parameter: <NR1>, Ex: +1
STATus:QUEStionable[:EVENt]?
Returns the total number of the Ouesrionable Event register.
Return parameter: <NR1>, Ex: +2
●An event register is a read-only register that latches events from the
condition register. While an event bit is set, subsequent events
corresponding to that bit are ignored.
●Once a bit is set, it remains set until cleared by reading the event register
or by sending *CLS (clear status).