R&S SMB100A User Manual

Remote Control Basics
R&S
®
SMB100A
272Operating Manual 1407.0806.32 ─ 21
Description of the five status register parts
The five parts of a SCPI register have different properties and functions:
●
CONDition
The CONDition part is written into directly by the hardware or the sum bit of the
next lower register. Its contents reflect the current instrument status. This register
part can only be read, but not written into or cleared. Its contents are not affected
by reading.
●
PTRansition / NTRansition
The two transition register parts define which state transition of the CONDition
part (none, 0 to 1, 1 to 0 or both) is stored in the EVENt part.
The Positive-TRansition part acts as a transition filter. When a bit of the
CONDition part is changed from 0 to 1, the associated PTR bit decides whether
the EVENt bit is set to 1.
– PTR bit =1: the EVENt bit is set.
– PTR bit =0: the EVENt bit is not set.
This part can be written into and read as required. Its contents are not affected by
reading.
The Negative-TRansition part also acts as a transition filter. When a bit of the
CONDition part is changed from 1 to 0, the associated NTR bit decides whether
the EVENt bit is set to 1.
– NTR bit =1: the EVENt bit is set.
– NTR bit =0: the EVENt bit is not set.
This part can be written into and read as required. Its contents are not affected by
reading.
●
EVENt
The EVENt part indicates whether an event has occurred since the last reading, it
is the "memory" of the condition part. It only indicates events passed on by the
transition filters. It is permanently updated by the instrument. This part can only be
read by the user. Reading the register clears it. This part is often equated with the
entire register.
●
ENABle
The ENABle part determines whether the associated EVENt bit contributes to the
sum bit (see below). Each bit of the EVENt part is "ANDed" with the associated
ENABle bit (symbol '&'). The results of all logical operations of this part are passed
on to the sum bit via an "OR" function (symbol '+').
ENABle bit = 0: the associated EVENt bit does not contribute to the sum bit
ENABle bit = 1: if the associated EVENt bit is "1", the sum bit is set to "1" as well.
This part can be written into and read by the user as required. Its contents are not
affected by reading.
Sum bit
The sum bit is obtained from the EVENt and ENABle part for each register. The result
is then entered into a bit of the CONDition part of the higher-order register.
Status Reporting System

R&S SMB100A Specifications

General

Brand	R&S
Model	SMB100A
Category	Inverter
Language	English